The present invention relates to a pseudo random pattern generating device which generates, at high speed, a pseudo random pattern which repeats the same pattern on a cycle of 2.sup.n -1 bits.
In the field of digital communications there is a demand for a pseudo random pattern generating device which operates at a speed as high as 3 to 10 GHz. From the technical viewpoint, however, it is extremely difficult to achieve such a high-speed operation with conventional pseudo random pattern generating devices of the type employing a register system.
FIG. 1 shows an example of the arrangement of a conventional pseudo random pattern generating device using a memory system which can be implemented through utilization of relatively simple high speed technology alone.
The prior art example is shown to generate a pseudo random pattern continuously repeating a basic random pattern which is 2.sup.4 -1=15 bits long, for instance, "100110101111000". This example will be described in connection with the case where the patterns to be generated are stored in a pattern memory 11 in which one word is composed of four bits.
The 15-bit long basic random pattern "100110101111000" is split into 4-bit patterns, beginning with the leftmost four bits, and these split patterns are stored in the pattern memory 11. At address 0 is stored a 4-bit split pattern "1001", at address 1 a 4-bit split pattern "1010", at address 2 a 4-bit split pattern "1111", and at address 3 a 4-bit split pattern "0001" which is a combination of the rightmost three bits "000" of the 15-bit basic random pattern and the leftmost bit "1" of the same basic random pattern "100110101111000" of second occurrence. At addresses 4 to 6 are stored subsequent split patterns "0011", "0101" and "1110", respectively, and at address 7 is stored a split pattern "0010" which is composed of the rightmost two bits "00" of the basic random pattern of second occurrence and the leftmost two bits "10" of the basic random pattern of third occurrence. At addresses 8 to 13 are stored 4-bit split patterns into which the 15-bit basic random pattern is split in a similar manner. At address 14 is stored a 4-bit split pattern "1000" composed of the rightmost four bits of the basic random pattern of fourth occurrence.
Upon application of a clock C to an address counter 12, its count value which is incremented by one upon each counting of the clock C is provided to an address decoder 14 of the pattern memory 11, and a split pattern stored at the decoded address of the pattern memory 11 is read out therefrom and provided, as 4-bit parallel data, to a parallel-serial converter 15. The parallel-serial converter 15 converts the 4-bit split pattern into serial data and outputs it as a pseudo random pattern on a bitwise basis.
As the count value of the address counter 12 is incremented from 0 to 3 by the clock C, the split patterns "1001", "1010", "1111" and "0001" are read out of the pattern memory 11 in that order. By concatenating these four split patterns and outputting them in serial form, the basic random pattern "100110101111000" of first occurrence and the leftmost bit "1" of the basic random pattern of the next occurrence are output. Following this, the split patterns "0011", "0101", ... stored at addresses 4 to 14 are read out in a sequential order, thus creating a pseudo random pattern which provides the basic random pattern "100110101111000" in a repeating cyclic order.
On the other hand, a numerical value "14" is set, as a stop code indicating the last address of the pattern memory 11, in a register 16. The set value "14" and the count value of the address counter 12 are provided to a coincidence detector 17. When coincidence is detected between the count value of the address counter 12 and the set value "14", the coincidence detector 17 yields a coincidence detection signal, by which an AND gate 18 is enabled. The clock C, which occurs after the detection of coincidence, is provided via the AND gate 18 and an OR gate 19 to the address counter 12, clearing it to zero. Consequently, the readout of the split pattern "1000" from address 14 is followed by the split pattern readout operation which starts again at address 0.
By reading out the four 15-bit long basic random patterns from addresses 0 to 14 in a repeating cyclic order as described above, it is possible to produce a pseudo random pattern which repeats the same random pattern at intervals of 15 bits.
With the above-described prior art example, however, no continued repetition of the basic random pattern can be obtained unless an integral number of the basic random patterns are stored in the pattern memory 11 so that the last bit in the last one of that number of basic random patterns locates at the rightmost bit position of the 4-bit word read out from the last address. For example, as shown in FIG. 1, the last bits (indicated by black triangles) of the basic random patterns stored in addresses 3, 7 and 11 do not occupy the rightmost bit positions of the split patterns stored at these addresses, and the last bit of a basic random pattern assumes the rightmost bit position of a split pattern for the first time at address 14 from which the rightmost four bits of the fourth basic random pattern are read out.
For example, in the case of successively generating a (2.sup.23 -1) bits long basic random pattern by reading it out, for instance, every 4-bit split pattern, it is necessary that at least four pseudo random patterns, which is an integral multiple of 4, be stored in a memory, and the required memory capacity therefor is (2.sup.23 -1) .times.4=8388607.times.4 bits, which is the least common multiple of (2.sup.23 -1) and 4; in this case, four standard 8-megabit memories are needed.
Such a large-capacity memory is usually formed by a MOS memory, and hence requires a read cycle time which is so long that the high-speed generation of the pseudo random pattern calls for increasing of the number of bits of each split pattern, that is, the number of bits of one word which is stored at each address. For example, where the number of bits of each split pattern is 256 bits, a memory of a capacity of 8 megabits .times.256 bits =2 gigabits is needed; in practice, however, it is difficult to implement such a large capacity.